The present invention relates to a semiconductor integrated circuit device, and in particular, to a technology effectively applicable to a semiconductor storage device having a vertical-type mask read only memory (ROM).
The semiconductor storage device having a mask ROM is advantageous in that the device is of a low cost and is satisfactorily safe against the destruction of information therein. The mask ROMs include a horizontal-type (parallel-type) mask ROM and a vertical-type mask ROM. The vertical-type mask ROM, as compared with the horizontal-type mask ROM, has a feature that a high integration is facilitated and hence a great amount of information can be accommodated.
In Japanese Patent Application Laid-Open No. 53-41188, filed by the present assignee, there is described a vertical-type mask ROM suitable for high integration. According to the vertical-type mask ROM, a plurality of gate electrodes of a first layer are disposed at a predetermined interval in the direction of the length of the gate, and gate electrodes of a second layer are formed between the gate electrodes of the first layer. The first-layer gate electrodes are formed from a polycrystalline silicon film of the first layer to establish memory cells each formed with an MIS capacitor or an MISFET. The second-layer gate electrodes are formed from a polycrystalline silicon film of the second layer, with the respective end portions of the second-layer gate electrodes overlying those of the first-layer gate electrodes, thereby establishing memory cells each formed with an MIS capacitor or an MISFET. The memory cells can be considered to be formed with an MIS capacitor established between the gate electrodes and a substrate or with an MISFET in which the channel regions of the memory cells on both sides of the MIS capacitor are regarded as a source and a drain for an electric current. Each memory cell is therefore connected in series. In a space between the first-layer gate electrodes and the second-layer gate electrodes (i.e., between memory cells), there need not be disposed a semiconductor region for the source and drain regions. Consequently, the memory cell areas can be considerably reduced.